mirror of
https://github.com/emmansun/gmsm.git
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225 lines
4.5 KiB
ArmAsm
225 lines
4.5 KiB
ArmAsm
// Copyright 2024 Sun Yimin. All rights reserved.
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// Use of this source code is governed by a MIT-style
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// license that can be found in the LICENSE file.
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//go:build (ppc64 || ppc64le) && !purego
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#include "textflag.h"
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#define X1L V0
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#define X1H V1
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#define Y1L V2
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#define Y1H V3
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#define T1L V4
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#define T1H V5
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#define T0 V4
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#define T1 V5
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#define T2 V6
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#define SEL1 V7
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#define ZERO V8
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#define CAR1 V9
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#define CAR2 V10
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#define TT0 V11
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#define TT1 V12
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#define PL V30
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#define PH V31
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TEXT ·gfpNegAsm(SB),0,$0-16
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MOVD c+0(FP), R3
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MOVD a+8(FP), R4
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MOVD $16, R5
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LXVD2X (R4)(R0), Y1L
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LXVD2X (R4)(R5), Y1H
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XXPERMDI Y1H, Y1H, $2, Y1H
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XXPERMDI Y1L, Y1L, $2, Y1L
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MOVD $·p2+0(SB), R6
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LXVD2X (R6)(R0), PL
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LXVD2X (R6)(R5), PH
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XXPERMDI PH, PH, $2, PH
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XXPERMDI PL, PL, $2, PL
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VSUBCUQ PL, Y1L, CAR1 // subtract part2 giving carry
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VSUBUQM PL, Y1L, T1L // subtract part2 giving result
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VSUBEUQM PH, Y1H, CAR1, T1H // subtract part1 using carry from part2
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VSUBCUQ Y1L, PL, CAR1
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VSUBUQM Y1L, PL, Y1L
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VSUBECUQ Y1H, PH, CAR1, SEL1
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VSUBEUQM Y1H, PH, CAR1, Y1H
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VSEL T1H, Y1H, SEL1, Y1H
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VSEL T1L, Y1L, SEL1, Y1L
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XXPERMDI Y1H, Y1H, $2, Y1H
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XXPERMDI Y1L, Y1L, $2, Y1L
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STXVD2X Y1L, (R0+R3)
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STXVD2X Y1H, (R5+R3)
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RET
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#define gfpSubInternal(T1, T0, X1, X0, Y1, Y0) \
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VSPLTISB $0, ZERO \ // VZERO
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VSUBCUQ X0, Y0, CAR1 \
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VSUBUQM X0, Y0, T0 \
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VSUBECUQ X1, Y1, CAR1, SEL1 \
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VSUBEUQM X1, Y1, CAR1, T1 \
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VSUBUQM ZERO, SEL1, SEL1 \ // VSQ
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\
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VADDCUQ T0, PL, CAR1 \ // VACCQ
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VADDUQM T0, PL, TT0 \ // VAQ
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VADDEUQM T1, PH, CAR1, TT1 \ // VACQ
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\
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VSEL TT0, T0, SEL1, T0 \
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VSEL TT1, T1, SEL1, T1 \
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TEXT ·gfpSubAsm(SB),0,$0-24
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MOVD c+0(FP), R3
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MOVD a+8(FP), R4
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MOVD b+16(FP), R5
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MOVD $16, R6
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LXVD2X (R4)(R0), X1L
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LXVD2X (R4)(R6), X1H
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XXPERMDI X1H, X1H, $2, X1H
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XXPERMDI X1L, X1L, $2, X1L
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LXVD2X (R5)(R0), Y1L
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LXVD2X (R5)(R6), X1H
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XXPERMDI Y1H, Y1H, $2, Y1H
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XXPERMDI Y1L, Y1L, $2, Y1L
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MOVD $·p2+0(SB), R7
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LXVD2X (R7)(R0), PL
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LXVD2X (R7)(R5), PH
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XXPERMDI PH, PH, $2, PH
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XXPERMDI PL, PL, $2, PL
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gfpSubInternal(T1, T0, X1H, X1L, Y1H, Y1L)
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XXPERMDI T1, T1, $2, T1
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XXPERMDI T0, T0, $2, T0
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STXVD2X T0, (R0+R3)
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STXVD2X T1, (R6+R3)
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RET
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#define gfpAddInternal(T1, T0, X1, X0, Y1, Y0) \
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VADDCUQ X0, Y0, CAR1 \
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VADDUQM X0, Y0, T0 \
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VADDECUQ X1, Y1, CAR1, T2 \ // VACCCQ
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VADDEUQM X1, Y1, CAR1, T1 \
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\
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VSUBCUQ T0, PL, CAR1 \ // VSCBIQ
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VSUBUQM T0, PL, TT0 \
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VSUBECUQ T1, PH, CAR1, CAR2 \ // VSBCBIQ
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VSUBEUQM T1, PH, CAR1, TT1 \ // VSBIQ
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VSUBEUQM T2, ZERO, CAR2, SEL1 \
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\
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VSEL TT0, T0, SEL1, T0 \
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VSEL TT1, T1, SEL1, T1
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TEXT ·gfpAddAsm(SB),0,$0-24
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MOVD c+0(FP), R3
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MOVD a+8(FP), R4
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MOVD b+16(FP), R5
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MOVD $16, R6
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LXVD2X (R4)(R0), X1L
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LXVD2X (R4)(R6), X1H
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XXPERMDI X1H, X1H, $2, X1H
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XXPERMDI X1L, X1L, $2, X1L
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LXVD2X (R5)(R0), Y1L
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LXVD2X (R5)(R6), X1H
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XXPERMDI Y1H, Y1H, $2, Y1H
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XXPERMDI Y1L, Y1L, $2, Y1L
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MOVD $·p2+0(SB), R7
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LXVD2X (R7)(R0), PL
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LXVD2X (R7)(R5), PH
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XXPERMDI PH, PH, $2, PH
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XXPERMDI PL, PL, $2, PL
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VSPLTISB $0, ZERO
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gfpAddInternal(T1, T0, X1H, X1L, Y1H, Y1L)
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XXPERMDI T1, T1, $2, T1
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XXPERMDI T0, T0, $2, T0
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STXVD2X T0, (R0+R3)
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STXVD2X T1, (R6+R3)
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RET
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TEXT ·gfpDoubleAsm(SB),0,$0-16
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MOVD c+0(FP), R3
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MOVD a+8(FP), R4
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MOVD $16, R6
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LXVD2X (R4)(R0), X1L
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LXVD2X (R4)(R6), X1H
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XXPERMDI X1H, X1H, $2, X1H
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XXPERMDI X1L, X1L, $2, X1L
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MOVD $·p2+0(SB), R7
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LXVD2X (R7)(R0), PL
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LXVD2X (R7)(R5), PH
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XXPERMDI PH, PH, $2, PH
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XXPERMDI PL, PL, $2, PL
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VSPLTISB $0, ZERO
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gfpAddInternal(T1, T0, X1H, X1L, X1H, X1L)
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VOR T1, T1, X1H
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VOR T0, T0, X1L
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gfpAddInternal(T1, T0, X1H, X1L, X1H, X1L)
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XXPERMDI T1, T1, $2, T1
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XXPERMDI T0, T0, $2, T0
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STXVD2X T0, (R0+R3)
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STXVD2X T1, (R6+R3)
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RET
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TEXT ·gfpTripleAsm(SB),0,$0-16
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MOVD c+0(FP), R3
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MOVD a+8(FP), R4
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MOVD $16, R6
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LXVD2X (R4)(R0), X1L
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LXVD2X (R4)(R6), X1H
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XXPERMDI X1H, X1H, $2, X1H
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XXPERMDI X1L, X1L, $2, X1L
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MOVD $·p2+0(SB), R7
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LXVD2X (R7)(R0), PL
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LXVD2X (R7)(R5), PH
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XXPERMDI PH, PH, $2, PH
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XXPERMDI PL, PL, $2, PL
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VSPLTISB $0, ZERO
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gfpAddInternal(T1, T0, X1H, X1L, X1H, X1L)
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VOR T1, T1, X1H
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VOR T0, T0, X1L
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gfpAddInternal(T1, T0, X1H, X1L, X1H, X1L)
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VOR T1, T1, X1H
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VOR T0, T0, X1L
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gfpAddInternal(T1, T0, X1H, X1L, X1H, X1L)
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XXPERMDI T1, T1, $2, T1
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XXPERMDI T0, T0, $2, T0
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STXVD2X T0, (R0+R3)
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STXVD2X T1, (R6+R3)
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RET
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