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split rotl 19 to rotl 10 then rotl 9

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Sun Yimin 2024-09-06 13:28:12 +08:00 committed by GitHub
parent adc8702ad7
commit 66d356888b
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1 changed files with 4 additions and 6 deletions
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10
sm3/sm3blocks_ppc64x.s
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@ -127,8 +127,8 @@ GLOBL ·mask(SB), RODATA, $80
VOR b, b, TMP4 \
PROLD(TMP4, b, 9) \ // b = b <<< 9
VOR TMP1, TMP1, h \ // h = TT1
VOR f, f, TMP4 \
PROLD(TMP4, f, 19) \ // f = f <<< 19
PROLD(f, TMP4, 10) \
PROLD(TMP4, f, 9) \ // f = f <<< 19
PROLD(TMP3, TMP4, 9) \ // TMP4 = TT2 <<< 9
PROLD(TMP4, TMP0, 8) \ // TMP0 = TT2 <<< 17
VXOR TMP3, TMP4, TMP4 \ // TMP4 = TT2 XOR (TT2 <<< 9)
@ -184,8 +184,8 @@ GLOBL ·mask(SB), RODATA, $80
VOR b, b, TMP1 \
PROLD(TMP1, b, 9) \ // b = b <<< 9
VOR TMP4, TMP4, h \ // h = TT1
VOR f, f, TMP1 \
PROLD(TMP1, f, 19) \ // f = f <<< 19
PROLD(f, TMP1, 10) \
PROLD(TMP1, f, 9) \ // f = f <<< 19
PROLD(TMP3, TMP1, 9) \ // TMP1 = TT2 <<< 9
PROLD(TMP1, TMP0, 8) \ // TMP0 = TT2 <<< 17
VXOR TMP3, TMP1, TMP1 \ // TMP1 = TT2 XOR (TT2 <<< 9)
@ -362,9 +362,7 @@ end:
STXVW4X c, (R0)(R4)
STXVW4X g, (R16)(R4)
MOVD (R17)(digPtr), R4
VSPLTISW $12, d
STXVW4X d, (R0)(R4)
VSPLTISW $19, h
STXVW4X h, (R16)(R4)
RET